1. Field of the Invention
The present invention relates to a semiconductor device comprising a Fin field effect transistor, and a method for manufacturing a semiconductor device.
2. Description of the Related Art
Much attention has been paid to a Fin field effect transistor (hereinafter sometimes referred to as a “FinFET”) as a transistor offering a larger ON current and a smaller OFF current than a planar transistor. In the FinFET, a gate electrode is formed to stride across a projecting semiconductor region. A gate insulating film is formed between the gate electrode and the projecting semiconductor region. A part of the projecting semiconductor region which is located immediately below the gate electrode forms a channel region. A part of the projecting semiconductor region which is not covered with the gate electrode forms a source/drain region.
Two types of FinFET are available: a single-structure FinFET with one gate electrode and one source/drain region, and a multi-structure FinFET with a plurality of gate electrodes and a plurality of source/drain regions. Japanese Patent Laid-Open No. 64-8670 discloses a single-structure FinFET. Japanese Patent Laid-Open Nos. 2002-118255 and 2001-298194 disclose multi-structure FinFETs.
FIG. 1 illustrates a top view of a semiconductor device including a multi-structure FinFET with two gate electrodes. As illustrated in FIG. 1, the FinFET includes projecting semiconductor region 1 on a substrate. Two gate electrodes 2 are provided so as to stride across semiconductor region 1. A gate insulating film (not illustrated in the drawings) is provided between semiconductor region 1 and each gate electrode 2. Both parts of semiconductor region 1 sandwiching each gate electrode 2 form source/drain region 3. Semiconductor region 1, one gate electrode 2, the gate insulating film, and source/drain region 3, that is, a set of a source region and a drain region, form one FinFET. In FIG. 1, the source/drain region is shared by adjacent FinFETs.
FIGS. 2 to 12 are diagrams illustrating a process for manufacturing a semiconductor device including the FinFET. A in each of the figures denotes a cross section A-A′ of the FinFET in FIG. 1. B in each of the figures denotes a cross section B-B′ of the FinFET in FIG. 1. C in each of the figures denotes a cross section C-C′ of the FinFET in FIG. 1.
First, silicon semiconductor substrate 4 is prepared. A surface of silicon semiconductor substrate 4 is oxidized to form silicon oxide film 5. Then, a silicon nitride film is formed all over the resulting surface and then patterned by a lithography technique. The silicon nitride film is thereafter dry etched to form pattern 6 of the silicon nitride film. This step covers the silicon semiconductor region (active region) with pattern 6 of the silicon nitride film and forms a shape in which a part of silicon semiconductor substrate 4 corresponding to an isolation region is exposed (FIG. 2).
Then, pattern 6 of the silicon nitride film is used as a hard mask to dry etch silicon oxide film 5 and silicon semiconductor substrate 4. The dry etched part of silicon semiconductor substrate 4 is thereafter oxidized to grow a silicon oxide film. The silicon oxide film is then subjected to a CMP process to form isolation region 7 (FIG. 3).
Then, pattern 6 of the silicon nitride film is removed. Thereafter, a silicon nitride film is newly formed on a part of silicon semiconductor substrate 4 on which isolation region 7 has not been formed. The silicon nitride film is then patterned by the lithography technique. The silicon nitride film is thereafter dry etched to form mask pattern 8 of the silicon nitride film. Silicon oxide film 5 is then removed by dry etching using mask pattern 8 of the silicon nitride film as a mask. At this time, silicon semiconductor substrate 4 is exposed (FIG. 4).
In this case, a surface of the exposed part of silicon semiconductor substrate 4 may be degraded by etching. Thus, sacrifice oxide layer 9 is formed on the exposed part of silicon semiconductor substrate 4 (FIG. 5).
Then, the sacrifice oxide layer is removed by wet etching to expose silicon semiconductor substrate 4 (FIG. 6). Impurities for a channel region are thereafter implanted into silicon semiconductor substrate 4 through mask pattern 8 of the silicon nitride film as a mask to form impurity region 10 (FIG. 7). Thermal oxidation based on ISSG (In Situ Stream Generation) is thereafter performed to form an oxide film all over the resulting surface. Gate insulating film 18 is thus formed on exposed silicon semiconductor substrate 4.
DOPOS (DOped POlycrystalline Silicon) is thereafter grown to form polysilicon film 11 all over the resulting surface (FIG. 9). Polysilicon film 11 is then subjected to a CMP (Chemical Mechanical Polishing) process using mask pattern 8 of the silicon nitride film as a stopper.
Then, W (tungsten) film 12 and silicon nitride film 13 are deposited all over the resulting surface (FIG. 10). A part of polysilicon film 11 and a part of W film 12 are allowed to react with each other (silicidized) to form WSi film 14 on polysilicon film 11, on which W film 12 is left. Thus, a gate electrode made up of a laminate structure of the W layer, WSi layer, and polysilicon layer is formed.
Then, the first mask 15 is formed on the gate electrode. A process of forming the first mask 15 involves, for example, depositing a silicon nitride film all over the resulting surface, and then patterning the silicon nitride film using the lithography technique so as to leave the silicon nitride film only on the gate electrode to form the first mask 15.
Then, W film 12 on the mask pattern is removed through the first mask 15 as a mask. Protect film 16 is formed all over the resulting surface (FIG. 11). The resulting surface is then entirely etched back to remove mask pattern 8 and protective film 16 on mask pattern 8 so as to leave the first mask 15 on the gate electrode. Impurities are then implanted into silicon semiconductor substrate 4 through the first mask 15 as a mask to form source/drain region 17 (FIG. 12).
We have now discovered that with the above-described method for manufacturing a semiconductor device, the width of the projecting semiconductor region, composed of the part of the semiconductor substrate surrounded by the isolation region, is reduced by formation and subsequent removal of the sacrifice oxide film on exposed silicon semiconductor substrate 4. Furthermore, implantation of the impurities for the channel region is thereafter performed. Thus, for example, as shown in FIG. 7, the impurities for the channel region are implanted not only in the projecting semiconductor region but also even around lower part 19 of the projecting semiconductor region.
Since the impurities are implanted even around lower part 19 of the projecting semiconductor region, various problems have occurred in connection with the characteristics of the Fin field effect transistor. That is, when N-type impurities are implanted into an N-type Fin field effect transistor as shown in FIG. 7, a possible off current (leakage current) from lower part 19 of the projecting semiconductor region increases. Furthermore, when P-type impurities are implanted into the N-type Fin field effect transistor as shown in FIG. 7, an electric field gradient between the channel region and the drain region increases and thus a possible junction leakage current increase.
Moreover, when the P-type impurities are implanted into a P-type Fin field effect transistor as shown in FIG. 7, the possible off current (leakage current) from lower part 19 of the projecting semiconductor region increases. Furthermore, when the N-type impurities are implanted into the P-type Fin field effect transistor as shown in FIG. 7, the electric field gradient between the channel region increases and the drain region and thus the possible junction leakage current increase.
Furthermore, since the impurities are implanted even around lower part 19 of the projecting semiconductor region, the amount of impurities implanted in a part serving as the channel region correspondingly decreases while the field effect transistor is on, by the amount of impurities implanted in the lower part. As a result, strict control such as an advance increase in the amount of implanted impurities is conventionally required to implant a desired amount of impurities in the part serving as the channel region.